This invention relates to computers designed with commercially available microprocessor chip sets. More particularly, the present invention relates to personal computers in which commercially available microprocessor chips are used and compatibility is maintained with existing application programs which were designed for use on personal computers employing incompatible microprocessor chip sets.
Popular microprocessor chip sets widely used by microcomputer manufacturers include the 8088, the 8086 and the 80286 microprocessors, all manufactured by Intel Corporation (hereafter "Intel"), and having similar instruction sets. Similar instruction sets are also available for a later generation microprocessor from Intel, namely, the 80386 microprocessor. Intel also produces a coprocessor chip, the 80287, which may be used either with the 80286 or the 80386 microprocessor chips to achieve even higher execution throughput rates. The 80286 and 80386 microprocessor chips are fully described in the "Microprocessor and Peripheral Handbook", published by Intel Corporation, 1987, and is incorporated by reference as if fully set forth herein.
Among the features of the 80286 is extended address space in the so-called "protected" mode of the microprocessor (hereafter also "central processing unit", "CPU" or "processor"). However, application programs which use the extended address space in the protected mode can return to the so-called "real" mode of the microprocessor only by resetting the microprocessor by generating a microprocessor RESET cycle. In the 80286 microprocessor, resetting the microprocessor does not disturb the state of the rest of the personal computer system (hereafter also "microcomputer" or "system") because many other types of operations can occur while the CPU is being reset.
Operations can occur during a microprocessor RESET cycle in microcomputers utilizing the 80286-type microprocessor because that type of microprocessor recognizes and retains a HOLD request from microcomputer subsystems external of the microprocessor itself during a microprocessor RESET cycle. Thus, system direct memory access (DMA), bus master and system memory refresh (REFRESH) operations, all of which utilize the HOLD request command, can occur while the CPU is being reset. This feature in the 80286 microprocessor, namely to recognize a HOLD request during a RESET cycle (hereafer "HOLD-during-RESET" feature), was eliminated in the 80386 microprocessor chip. Thus, in this respect, the 80386 chip clearly is not compatible with the 80286 microprocessor chip.
Many computer programmers took advantage of the ability of the 80286 microprocessors to run application programs in so-called "real" and "protected" modes and implemented this capability while developing applications software packages. Thus, many applications software packages designed for use on microcomputers using an 80286 microprocessor chip utilize the HOLD-during-RESET feature. Those programs therefore, are also incompatible for execution on any microcomputer utilizing the 80386 microprocessor chip.
In order to assure continued commercial demand for already developed applications software packages and to enhance the demand for computers using the 80386 microprocessor chip, means for making programs written for microcomputers utilizing the 80286 microprocessor compatible with microcomputers utilizing the new 80386 microprocessor is necessary. Of course, such means should provide the needed compatibility to execute a majority of the applications without having to reprogram the software packages to execute on microcomputers using the 80386 microprocessor, or to redesign the 80386.
In the pertinent prior art, U.S. Pat. No. 4,787,032 describes a circuit and related logic for arbitrating microprocessor access during a RESET cycle. As described, the circuit and logic retains the HOLD request until the RESET cycle has been completed or, conversely, if a HOLD request is being processed when a RESET cycle is requested, the RESET request is retained until the HOLD request has been completed. Thus, if used with the circuit and logic described, the 80386 may be reset without losing a HOLD request. However, the teaching of U.S. Pat. No. 4,787,032 arbitrates all RESET and HOLD requests uniformly without regard to the nature of the operations utilizing HOLD request commands.
In microcomputer systems which utilize the HOLD-during-RESET feature, memory REFRESH, DMA slave and bus master operations all utilize the HOLD request command. While such operations must wait for completion of a microprocessor RESET operation, it is not desirable to force a memory REFRESH operation to wait for completion of a DMA slave or bus master operation. Even if user data or program information is not actually lost, delay of a memory REFRESH operation at least jeopardizes the integrity of and timely access to such data or information.
Therefore, it is desirable to provide a microcomputer with a later generation microprocessor which is capable of executing applications software programs written for earlier generations of microcomputers using the older generation microprocessors. In addition, it is desirable to provide such a microcomputer without having to redesign the new CPU chip or reprogram applications software packages. Finally, it is also desirable that in such a microcomputer, the integrity of user data and program information is neither lost or jeopardized by the method and apparatus for achleving such compatibility.